Forming integrated circuits on a semiconductor substrate includes photolithographic patterning processes. The semiconductor substrate is coated with a photoresist material that is sensitive to an exposure radiation. The exposure radiation such as an ultraviolet ray, an electron beam or a X-ray is irradiated onto the photoresist layer for example through a mask or a reticle, wherein the photoresist layer is selectively exposed to the exposure radiation. After exposure, the film is developed to form a photoresist pattern in accordance with or contrary to the mask pattern. The photoresist pattern may be used as an etching mask in the following.
Resolution enhanced techniques (RETs) improve the resolution of optical lithographic systems. For example, evenly spaced parallel line structures may be formed at a pitch that is smaller than a pitch that corresponds to the nominal resolution limit of the lithographic system. In the following, “F” corresponds to a minimum lithographic feature size describing the half pitch of the lines in the densest line field that can be achieved through common RETs. “F” may be in the range of 20 to 140 nanometers. Pitch-fragmentation methods may allow to half the pitch in a dense line field such that, for example, the gate, supply, and data lines of sensor or memory cell arrays may be arranged at a pitch of F.
A need exists for a further shrinkage of the minimum pitch of dot-shaped semiconductor structures, for example buried structures, in two-dimensional arrays and one-dimensional chains of dot-shaped structures.